Flat panel display devices are widely used for image displays. Flat panel display devices include liquid crystal displays (LCD), plasma display panels, and electroluminescent displays. Flat panel displays can replace bulky displays, such as cathode ray tubes (CRT). In particular, LCD devices have been widely used as replacements for bulky CRT displays.
FIGS. 1A-3A are top plan views illustrating a conventional LCD device during intermediate fabrication steps, and FIGS. 1B-3B are cross-sectional views taken along the line 1B-1B' through 3B-3B' of respective FIGS. 1A-3A. As shown in FIGS. 1A and 1B, a metal layer, such as chromium (Cr), aluminum (Al) or tantalum (Ta), is formed on a substrate 10. A first patterning step is performed to form a patterned gate layer 11 from the metal layer. The patterned gate layer 11 is used to define a gate electrode for a thin film transistor (TFT). The patterned gate layer may also define gate wiring, a gate pad electrode, additional capacity electrodes, and other elements.
Still referring to FIGS. 1A and 1B, an insulating layer 13 is formed on the surface of the substrate 10 including on the patterned gate layer 11. A semiconductor layer comprising an amorphous silicon layer 15 and a doped amorphous silicon layer 17 is then formed. A second patterning step is then used to pattern the semiconductor layer, to form a semiconductor layer pattern 19. The semiconductor layer which is formed on a gate pad electrode (not illustrated) is also patterned. It will be understood that patterning may be performed using photolithography and/or other conventional microelectronic patterning techniques.
Referring now to FIGS. 2A and 2B, a conductive layer such as indium tin oxide (ITO) is formed on the substrate. Then, a third patterning step is performed to form pixel electrode 21. A metal, such as Cr, Al or Ta is then formed on the surface of the substrate 11. A fourth patterning step is then performed to form a data line 23a, a source electrode 23b and a drain electrode 23c. It will be noted that doped amorphous silicon layer 17 is also etched, to thereby partially expose the undoped amorphous silicon layer 15 over the patterned gate electrode 11.
Referring now to FIGS. 3A and 3B, a passivation layer 25 is formed on the substrate and a fifth patterning step is performed. In this step, the passivation layer 25 formed on the pixel electrode 21 is etched and the passivation layer 25 and the insulating layer 23 formed on the gate pad electrode (not shown) are also etched. Reference number 27 of FIG. 3A illustrates the region of the passivation layer 25 which is etched.
Unfortunately, as described above, conventional methods of fabricating LCD devices generally require at least five patterning steps. As is well known, the number of patterning steps can increase manufacturing costs and reduce manufacturing yields.